To cope with the ever-increasing power demands of VLSI chips, researchers are looking to circuit technologies that use reversible logic to conserve power
Peter Wayner
Over the next decade, the amount of power that's consumed by computer chips is likely to become one of the biggest headaches for chip designers and end users alike. Many VLSI designers hope to lower power consumption in two ways: by pushing well-known power-saving tricks to new levels and by dramatically retooling the fundamental structure of VLSI to let it recycle power by reversing the results of circuit-based operations. The first approach is common; the second approach is just appearing.
Two complementary forces are behind the drive to limit power consumption in microprocessors. One is heat; as processors get bigger and faster, the heat they dissip
ate increases proportionally. If ignored, this heat can literally melt the components of a system. The second force is the explosion of the use of portable computers, which depend on batteries to get through their day. The less power their chips use, the longer these portable devices can run.
Powerful Lessons
In the past, power use by computer chips was a problem that was often either pushed aside or solved with brute force. Mainframe and supercomputer manufacturers routinely traded high-power consumption for speed and found themselves creating specialized cooling systems for their machines. Both Cray and IBM built refrigerators into their big machines to remove the heat produced by the large amounts of power consumed by the CPU.
As has become apparent in recent years, microcomputer manufacturers are not immune to power problems. As microprocessors have got bigger and faster, cooling fans have proved insufficient to deal with all the power such chips dissipate as heat. Heat sinks are now de r
igueur on powerful chips, as are multiple fans and sophisticated case designs that help keep air circulating across hot components.
Moreover, people are discovering that the power use of personal computers is significant. The Wall Street Journal estimates that computers are responsible for 5 percent of a typical business's electric bill. In the summer months, the companies pay again when they run air conditioners to remove the heat generated by their computers. And, while they gain some heat from them in the winter, electrical heating is not economically competitive with gas or oil heat.
For notebook computers, power-consumption issues are, in many instances, insurmountable. No one makes Pentium-based notebook computers because no one can make a reasonable-size battery to keep such systems in operation for more than a few minutes. As portable computers become more indispensable, we need to be able to use the latest and most powerful processors in them.
Where the Power Goes
The physics
of power consumption in VLSI circuits is straightforward. A transistor switch consists of two wires. The flow of current through one wire is switched on or off by a packet of charge on the second. A microprocessor consists of millions of transistors that are turned on and off many millions of times per second. Every time one of these transistors is turned off, the electrons that were stuck on one wire to switch the flow of the second are sent to the grounding wire. In the process, heat is generated and power is consumed or dissipated.
Many factors influence the amount of power consumed, for both well and ill. The push for miniaturization has the nice side effect of reducing the power consumed by chips. Smaller transistors need less power because they require fewer electrons to saturate the wire that controls the flow. The smaller amount of power consumed by each transistor means that doubling or quadrupling the number of transistors does not double or quadruple the amount of power used.
The push
for greater speed, however, does increase the amount of power consumed. Each operation in a microprocessor must flip a certain number of transistor switches, and each flip consumes electrons. Doubling the clock speed doubles the amount of power consumed.
The quest for speed also has another effect on power consumption. If you want each transistor to switch quickly, you must use more electrons to make sure that the transistor becomes saturated as quickly as possible. This means that faster computers must use more charge per transistor flip. Therefore, doubling the speed of a chip may actually require more than twice as much power.
Reversing the Computation
Today, chip makers and computer manufacturers employ a number of well-known techniques to lower the power consumption of microprocessor-based systems (see the text box ``Low-Power Chip Technology''). These techniques will certainly lower the power consumption of chips significantly over the next several years, but they'll reach a natural li
mit when the voltage levels on the chip drop to the point where signal levels are indistinguishable from noise. Many physicists estimate that this point will be reached when voltage levels hit the range of 0.5 to 1.2 V.
At the industrial labs of IBM, Xerox, and AT&T, some scientists are attempting to reduce power consumption by recycling the power and reversing the computation. This work started when Rolf Landauer and Charles Bennett of IBM wrote theoretical papers showing that there is no minimum barrier to power consumption if the work in a VLSI circuit is done in a reversible way.
The idea of a reversible computation is straightforward. A system is reversible if no information is lost along the way. In a VLSI circuit, this means that all the extra charge that represents bits normally lost in combinatorial-logic AND and OR gates must be kept around so the system can be reversed. For example, if you're going to compute 2+2, a reversible system would pass on 4 as the answer, as would a standard
one. But a reversible system would also save at least one of the operands so it could reverse the computation. If it didn't, then it wouldn't know if the two operands were 1 and 3, 2 and 2, or 0 and 4.
In theory, when a computation finishes, a reversible chip would copy over the answer and then work its way backward. The copy operation would dissipate some energy, but the process of reversing the computation would return most of the charge to its original location. That would save much of the dissipated energy by recycling it.
Many people are skeptical of this entire process of reversing the mechanism because it seems more at home in a Rube Goldberg contraption than in a physics textbook. What's important to realize is that the standard method of building VLSI switches is very crude: It is equivalent to placing a car at the top of a cliff and pushing it off. The computation of switching a bit from 1 (the top of the cliff) to 0 (the bottom of the cliff) works, but all the stored energy is dissipa
ted at the bottom.
On the other hand, if the car was at the top of a steep hill instead of a cliff, it would roll down to the bottom and pick up sufficient speed to carry it up the other side. Some energy would doubtlessly be lost to friction in the system, but much less would be lost than if the car fell off a cliff. The process of running the car up the opposite side of the hill is the functional equivalent of putting a computational system in reverse. The trick is timing the system so that the results of the computation are captured at the point that's equivalent to when the car is at the bottom of a steep hill.
Slow Down and Conserve
Many physicists were also skeptical of the notion of reversible computation until 1992, when a number of different scientists, including Bill Athos of the University of Southern California (Marina del Rey), Josh Hall of Rutgers University (New Brunswick, NJ), and Ralph Merkle of Xerox PARC (Palo Alto, CA), developed a model showing how to convert standard CMO
S circuits into low-power reversible ones. The basic concept is to move charge gradually instead of instantaneously. This limits power dissipation and allows the charge to be recycled effectively.
Consider, for example, two ways to charge a capacitor--a simple model of the process of switching a transistor. In one case, the voltage is raised gradually over a period of time T. In the other, it is switched on instantaneously. In the first case, the power dissipated is also governed by a factor that is inversely related to the time it takes to charge the capacitor. The same model works when a capacitor is discharged.
This extra factor of T makes a big difference. If you slow down each gate by a factor of T, you use a factor of T less power. The chip also uses a factor of T less power per second because it is doing a factor of T less computations. This means that a reversible chip would save a factor of T2 power, but it would do a factor of T less computations.
At this point, physicists doing
reversible computation like to propose putting T circuits on the chip, which operate in parallel. If everything works perfectly, then you should have a total of T circuits, each doing 1/T work using 1/(T2) power. The net result is that the same amount of work could get done while cutting the power used by a factor of T.
There are several barriers to actually putting T circuits on a chip. First, the packing density of transistors on a chip must increase. This is not a major concern because the packing density has been steadily increasing since the development of the IC over 30 years ago. In fact, some physicists estimate that power consumption, not packing density, is becoming one of the main limitations of the size of current chips. Still, a circuit that uses a factor of T less power must consume at least a factor of T more silicon if it is to run at the same rate. In addition, there is a natural limit to the amount of parallel structure in a circuit that can be exploited by designers.
Recycling
the Charge
Although circuits that are loaded and unloaded at a slower rate dissipate less power, they still must move a charge from one place to another. A true low-power chip must find a way to recycle the power by reversing the computation. There are many different proposed solutions in this new field of study.
One simple approach, called SCRL (Split-Level Charge-Recovery Logic), was co-developed by Saed Younis and Tom Knight of MIT. The idea is to create a mirror image of a circuit that computes the inverse of the original. As each stage in the circuit finds its answer, it passes the result on to its mirror image, which computes the inverse. In the main circuit, charge moves toward the end, while in the mirror circuit, charge is recycled back to the beginning.
The figure ``Recovering Charge'' illustrates such a circuit. Each circuit in the line starts its computation just after the one before it. The idea is to switch the transistors when the voltage gap is low or nonexistent. Then when
the clock pulse rises, the switch will already be open and the power will flow gradually across a small voltage gap. The size of this gap determines how much power is lost as heat.
Since there must be a mirror image of the circuit constructed to return the charge, this approach doubles the number of transistors that are needed to implement a piece of logic. The chip designer must also create multiple clock lines that run each level of transistors at different times. This also complicates the design.
Other developers are using a more practical approach to the reversible-logic problem. A team of scientists (Stephen Avery, John Denker, Alex Dickinson, Alan Kramer, and Thomas Wik) at AT&T's Bell Labs in Holmdel, New Jersey, report that they have successfully built and tested a circuit consisting of 1000 inverters using a different formation of gates that does not contain an array of circuits mirroring the main gates.
In their simulations, they show that their inverters consume a third less po
wer because they switch themselves gradually. This design is less pure because it loses some information--and thus some power--but they estimate that a few circuits built with this approach will actually be smaller than their high-powered cousins.
At this point, it is difficult to guess what approaches will succeed in producing reversible-logic circuits. With new people approaching the topic all the time, the designs will undoubtedly change significantly in the next few years as the technology moves toward the marketplace.
The Clock Problem
No matter what approach you take toward reversible logic, the most difficult problem is finding a way to construct stable clock circuits that will drive the different circuits in the chain. Ideally, the results of the computation will gradually propagate down a chain of gates, with each gate performing its work just after the gate before it completes its work. In a sense, the computation travels along the circuit in much the same way that Tarzan swings amo
ng the trees on vines. As long as the clocks (or the vines) are in the correct phase, then everything moves smoothly.
VLSI circuit designers are not experienced with designing clocks that move gradually up and down. Most current VLSI chips provide clock circuits that make abrupt changes when the clock ticks. Creating new ones that produce gradual swings in voltage is a challenge.
This challenge is important, because the speed and continuity of the clock signal will directly affect the consumption of power throughout the chip. Any sudden jumps in voltage will dissipate power throughout the chip. More important, there must be a separate signal for each of the successive parts of the circuit. If any of these clock signals gets out of phase, there is a slight voltage gap between the gates. Power disappears across these gaps.
The Future
In the near future, chip designers will need to pay more attention than ever to the power requirements of chips. Already there are indications that some des
igners are sacrificing additional cache and floating-point performance to keep power consumption in line.
Over the next 10 years, chip designers will continue to pursue a variety of different approaches to lowering power consumption. Lowering the operating voltage and slowing the chips will be popular solutions, because they offer substantial power savings and do not require the adoption of radically new circuit designs.
Reversible logic offers to lower the cost of computing independently of changing the voltage. More important, when these circuits slow down, they save power based on the square of the speed loss. The overall speed of the circuits can be maintained, but the cost will certainly be larger circuits. However, this may be much more desirable than putting built-in refrigeration units on microcomputers.
There is much debate about the limit to the amount of power that can be saved with reversible computation. Many scientists actively pursuing reversible-logic research think that a
factor of 10 in power savings is a conservative estimate; some are willing to offer up the hope of a factor as high as 100 to 1000. But one thing is certain: As low-power chips become more important, there will be lots of opportunities to try many different approaches.
FOR FURTHER READING
Illustration: The Logic of Reversible Logic
Chips today consume so much power because of the way in which transistors switch on and off. When a transistor switches from a high-logic state to a low-logic state, all the energy required to get to the high state is dissipated, just like a car going over a cliff dissipates its potential energy at impact. Reversible logic aims to conserve the energy so that it can be used to switch again.
Figure: Recovering Charge
With split-level charge recovery, circuits are paired with their inverse ci
rcuits (1 with 6; 2 with 5; 3 with 4). The results of the main circuit chain are passed to the mirror-image chain, thus preserving the results and the energy used to generate them. The timing diagram shows how the clocks that drive the circuits must cascade so that the system uses as little power to switch as possible.
Peter Wayner is a BYTE consulting editor based in Baltimore, Maryland. He can be reached on the Internet at
pcw@access.digex.com
or on BIX as ``pwayner.''
Silicon in Reverse
