Video Architectures

a) Dual Frame Buffer
In a dual-frame-buffer architecture, the video-acceleration b oard plugs into the host system's I/O bus and connects to an existing graphics adapter via the feature connector. Each accelerator uses its own video memory and DAC (D/A converter). The feature connector limits screen resolution to 640 by 480 pixels and suffers from incompatibilities with some board combinations.
b) Shared Frame Buffer
With a shared-frame-buffer interface, the graphics accelerator and video processor share one video-memory buffer, lowering memory requirements. Both accelerators feed the buffer, and each requires its own controller to arbitrate access to video memory.
c) Single Frame Buffer
A single-frame buffer routes converted video data through the graphics controller. All the display data--video and graphics--is then stored in the frame buffer. No buffer arbitration is needed because the graphics controller alone feeds the buffer. The single-frame-buffer architecture also requires only a single communications port to video memory, so in expensive DRAM can be used instead of dual-ported video memory.