Graphics Glossary

BITBLT

Stands for bit block transfer, a hardware-based process that moves a rectangular block of bits from main memory into display memory.

BLTING

A straight-pixel copy from video memory to the screen.

HARDWARE PANNING

A technique that allows you to pan across a large desktop more quickly than if you were using the normal interface.

MODE SWITCHING

The toggling between screen resolutions and pixel depths. Some video cards have special drivers that allow them to switch modes on the fly (i.e., without restarting Windows).

NUBUS

This 32-bit architecture is a self-configuring bus design used in Macintosh systems for peripheral expansion.

PCI

Stands for Peripheral Component Interconnec t; a 32- or 64-bit local-bus design that uses a hardware layer that isolates the CPU and, therefore, is processor independent. It operates at 33 MHz rather than the speed of the processor. PCI devices are self-configuring.

REFRESH RATE

The number of times a display screen is redrawn per second. The higher the rate, the less flicker a display presents.

RESOLUTION

The number of pixels that can be activated on-screen at one time, expressed in the horizontal value by the vertical value (e.g., 1024 by 768).

64-BIT VS. 32-BIT INTERLEAVED

A 64-bit graphics accelerator uses a 64-bit data path to video memory. The 32-bit interleaved controller uses two passes to load data into odd and even banks of memory. While one bank is in precharge, the interleaved controller performs data I/O on the other.

SRAM

Stands for static RAM; describes chips that do not require a refresh cycle, as DRAM chips do, and thus can be acc essed over twice as quickly. SRAM chips cost more than DRAM chips.

SVGA

Stands for Super VGA; originally referred to resolutions of 800 by 600 dpi at various color depths. Today, SVGA commonly refers to 1024- by 768-pixel resolution.

VRAM VS. DRAM

VRAM chips are true dual-ported memory chips that allow simultaneous reads and writes. A DRAM chip requires its content to be refreshed; read and write operations cannot occur simultaneously.