I read ``AMD vs. Superman'' (November 1994) and was wondering how the registers are selected for the r-ops (RISC operations). Are they predefined? If so, how do they interact with the compiler-generated ones? Wouldn't you need to introduce some additional registers to hold the temporary results?
Nader Bagherzadeh
nader@ece.uci.edu
AMD's K5 has twice as many physical GPRs (general-purpose registers) as a conventional x86 processor, and it dynamically renames those 16 GPRs to represent the architectural set of eight logical GPRs. Temporary/intermediate results are held in a physical register until validated, and then the physical register is renamed as a logical register. This is becoming a common technique in modern processors. It's also used in the Cyrix M1 and the Mips T5 (R10000). Basically, it's just a way of getting
around the limited register files of existing CPU architectures. --Tom Halfhill
Flexible C++
Matthew Wilson
My approach to software engineering is far more pragmatic than it
is
theoretical--and no language better exemplifies this than C++.
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RISC Registers
