Intel's P6 is the logical next step beyond the Pentium, but the P7 could introduce a radically different technology that achieves a breakthrough in performance while preserving backward compatibility. Then again, the P7 project could fall flat on its face.
Last year, Intel formed a much talked-about partnership with Hewlett-Packard to design a new microprocessor that is expected to appear in 1997 or 1998. The two companies are revealing little about this processor except that it will attempt to leapfrog RISC technology and run all existing software for Intel's x86 and HP's PA-RISC chips. In addition to supporting both of those legacy instruction sets, it will probably introduce a new instruction set of its own.
The prevailing rumor is that Intel and H
P are experimenting with a technology called VLIW (very long instruction word). Ironically, VLIW is almost exactly the opposite of the technology used by the P6. While the P6 contains a sophisticated decoder that translates complex x86 instructions into shorter, simpler RISC-like operations, a VLIW processor would rely on a new type of compiler to pack several simple operations into very long instructions. Each instruction packet would contain operations that aren't interdependent, so the CPU could rapidly execute them in parallel (see "VLIW Questions," November 1994).
In other words, a VLIW processor shifts the responsibility for instruction scheduling from the hardware to the software. The scheduling intelligence would be built into the compiler, which, in turn, would embed it into the applications software.
The compiler technology required to make this practical hasn't been perfected. Another problem is that software compiled for one version of a VLIW chip would probably have to be recompiled
for the next generation. Software vendors would make millions on upgrades, but users wouldn't be too happy.
For these and other reasons, some observers doubt that Intel and HP can produce a commercially viable VLIW chip. Because the x86 market is far too important for Intel to bet everything on an unproven technology, it is likely that Intel has a parallel project to develop a more conventional P7 in case the VLIW project fails.
There is still plenty of room for improvement in the x86 architecture. The P7 could be a four- to six-way superscalar machine with larger primary caches, an integrated secondary cache, more execution units, and larger buffers to support deeper paths of speculative execution. It could also speculate both ways beyond a predicted branch, a technique IBM tried in a 1960s mainframe.
Meanwhile, Intel's competitors aren't sitting still. NexGen plans to introduce the Nx686 by the end of this year and predicts two to four times the performance of the Nx586. Cyrix says it
is already working on successors to the M1, though no details have been disclosed.
AMD has mapped out its future in the most detail. The K5 will be followed by a K6 in 1996, with volume production in 1997. The K6 will be fabricated on a 0.35-micron process and is expected to have 6.5 million transistors; estimated performance is 300 SPECint92. In 1997, AMD plans to introduce a K7 that will ramp up to volume production in 1998 on a 0.18-micron process with 10 to 15 million transistors; it is expected to deliver 700 SPECint92 at 400 MHz. Finally, AMD is planning a K8 in 2001 that will have 20 million transistors and deliver 1000 SPECint92 at 600 MHz.
Additional competitors may surface, too. IBM Microelectronics, Texas Instruments, SGS-Thomson Microelectronics, and a few Asian companies already make 386 and 486 chips. So far, however, these companies have not committed themselves to the more difficult challenge of designing a state-of-the-art x86 processor that would compete directly against the la
test products from Intel, AMD, Cyrix, and NexGen.
The P7 and Beyond
