Smart Memory

The most sophisticated approach to squeezing more information out of memory chips is that being taken by Cray Computer (Colorado Springs, CO). Engineers are building a new version of the Cray 3 supercomputer using a special kind of memory that contains embedded processors. Each memory chip comes with 128 Kb of storage and 64 single-bit ALUs that can perform all the basic 1-bit operations. The 1-bit processors embedded on the Cray memory chips each contain three 1-bit registers. Data in any of the local bits of each processor can be loaded into and stored from these registers. Each of the three registers can have two different states, which means there are eight possible configurations for the set of registers. A programmer specifies an instruction for t he 1-bit ALUs by presenting an ALU with 1 byte that contains the 1-bit answer to all eight possible configurations. The chips were designed by the Supercomputer Research Center (Bowie, MD) as part of a research program sponsored by the National Security Agency, or NSA. The technology was licensed by both Cray Computer and National Semiconductor, who will be fabricating the chip.

This chip was designed to act like normal memory most of the time. If, however, the main processor wants to use any of the 64 processors scattered throughout the memory, it raises one of the signal lines and effectively writes the instruction to the chip. The instruction is dispersed to the individual processors, each of which executes the instruction on 2048 bits of local data.

The processors have a 1-D shift register for communicating with one another. In many respects, this is the most significant difference between this approach and the classic single-instruction, multiple-processor arrays like the Connection Machine CM-1. Those older machines used complicated 12-dimensional message-passing arrays to route data between processors. This limited the number of processors on each chip simply because there weren't enough pins in a standard package to handle a large 12-dimensional network.

The first computer system using this new memory will be known as the Cray 3/SSS, and the first customer is NSA, which will presumably use it for code breaking. Robert Cox, director of the Cray 3/SSS project, expects that the computer will find many uses in highly parallel problems (e.g., image processing and seismic computation).

Coherent Research (Syracuse, NY), a company that has manufactured and tested similar products, has shown how this specialized memory could be used in graphics accelerators. They produced a demonstration system that would identify which window was hit by a mouse, doing this by testing all the windows in parallel using the processor array embedded in the memory. Such highly parallel applications might be desirable, for instance, in future games that flash many different objects across the screen. With the ability to test for collisions and selection in parallel, game designers could add many objects to the screen without decreasing performance. This high-end memory could also have application in database searches, ray tracing, and other highly parallel problems.

In late March, the preceding was written before Cray Computer filed for Chapter 11 and laid off many employees. Obviously, the immediate future for this particular, and expensive, memory technology is uncertain, but the special demands of supercomputing may yet see it become a commercial reality.