I enjoyed your article "Intel's P6" (April); however, the P6 is not the first chip "intended for large-scale production" with two dies on a single package. That honor goes to the DEC J-11 11/70-on-chip. The J-11 was the first PDP-11 (maybe the first chip of any type) to be able to do register-to-register instructions in one cycle (200 nanoseconds), and it had a four-level pipeline, truly great accomplishments in 1982.
Bob Morris
President
DSPS Digital Signal Processing, Inc.
Carleton University
Ottawa, Ontario
morris@sce.carleton.ca
I really enjoy the depth to which BYTE explores topics like the P6. I still have a few questions regarding your April Cover Story. On what front-end bus speed (1/2 CPU, 1/3 CPU....) does Intel base the P6's performance numbers? Also, I was under the impression that a 100-MHz Pentium really runs at
99 MHz. This would make it easy to use a PLL (phase-locked loop) to create 66 MHz for the main bus. It follows that the P6 would use a 132-MHz clock rate so the main bus would run at 66 or 33 MHz.
Karl Richards
richardk@execpc.com
The P6's I/O (i.e., frontside) bus can be clocked at 1/2, 1/3, or 1/4 of the core speed. The performance estimates from Intel are based on a system that runs internally at 133 MHz and externally at 66 MHz. In other words, 1/2 clock speed. It doesn't make sense to run a 133-MHz P6 at 1/3 or 1/4--those dividers were included for future P6 chips that will run at faster core speeds. My understanding is that a 100-MHz Pentium actually runs at 100 MHz, not 99 MHz, and that a 133-MHz P6 runs at 133 MHz, not 132 MHz.
--Tom R. Halfhill
In your April Cover Story you describe the physical dimensions of the current crop of processor chips as "306 mm square." That comes very close to being a foot on a side. We'll have to redesi
gn all our personal computers just to hold the CPU. This is too much!
Merritt J. Rucher
Belen, NM
Yes, the size was supposed to be written as "square millimeters," not "millimeters square," but somehow it got transposed.
--Tom R. Halfhill
Intel's P6
