Two things consume board space: parts and traces. The two-chip Basic Stamp reduces the parts count about as far as you could -- or would want to -- go. Minimizing traces is another matter; you have to be able to get data back and forth between the chips.
That's where serial chips help. For example, the 93LC56 serial EEPROM holds 256 bytes, which for most EPROMs would mean eight data lines and eight address lines to the host CPU. On the 93LC56, that's all handled by four wires: one for chip selection, another for the clock signal, and two more for data in and out. A clever designer can multiplex data in and out, bringing the number of wires down to three.
To read a byte, the CPU sends a command packet to the EEPROM. This command consists of a read op c
ode, followed by the address bits. The EEPROM decodes the command and responds with the 8-bit contents of the requested address. A similar protocol controls write operations. Bits flowing along the data line are synchronized by the clock signal.
Transfers between the CPU and EEPROM can be as fast as 2 Mbps. This is a lot slower than a conventional bus, but plenty fast considering the board-space savings.
Bit Flow
illustration_link (5 Kbytes)
Serial Chips
