By handling memory transfers for the CPU, a good direct memory access (DMA) system improves overall performance. Still, moving large blocks of data between memory and a device, or vice versa, requires multiple DMA transfers. Typically, each transfer ends in an interrupt to the CPU, which must then drop what it's doing to set up the next transfer. To manage its 14 DMA channels without this overhead, the 9500 employs a descriptor-based DMA engine.
Descriptors serve as a simple instruction set for implementing DMA transfers. Glue logic around the DMA controller executes the instruction set, which supports branching, looping, and error handling. Each descriptor is a four-long-word data block with 16- and 32-bit fields that include the command, requested data
size, buffer address, a device-specific instruction, status, information, and the resulting amount of data moved. Not all commands use all fields. By chaining descriptors into a mini-program, descriptor-based DMA moves large data blocks without interrupting the CPU.
Taking advantage of descriptor-based DMA requires device-driver modification. The driver must parse each I/O request for size and location and then place in memory sufficient descriptors to handle the transfer. SCSI, Ethernet, sound, serial, and floppy subsystems use this capability to reduce CPU overhead in the 9500.
Chaining DMA Won't Hold it Back
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By chaining DMA descripto
rs to describe and execute DMA transfers, the 9500 reduces CPU overhead.
Smarter DMA
