Next generation: UltraSparc-II
DOSSIER:
An early adopter of RISC technology, Sun specified SPARC in 1988 as a scalable, "future-proof" architecture. However, by 1993, the SuperSparc implementation had begun to lag badly behind its competitors.
The UltraSparc, the fourth SPARC generation, will make up much of that lost ground. It contains no less than nine execution units: two integer ALUs, five FPUs (two for floating-point addition, two for floating-point multiplication, and one for floating-point division/square roots), a branch-processing unit, and a load/store unit. The UltraSparc has dynamic branch prediction integrated into its primary instruction cache and speculatively executes predicted branches, bu
t it cannot issue instructions out of order. It relies on optimizing compilers to order them well.
The SPARC architecture has always offered register windows, eight overlapping banks of 24 duplicate registers that can preserve the processor state during context switches instead of doing an expensive write to memory. Compiler writers have often found these windows insufficient, so the UltraSparc adds an extra mechanism whereby a fresh window of eight registers becomes available every time an interrupt, memory management unit (MMU), or other trap occurs. This should greatly speed up the handling of multithreaded code.
To get high sustained system bandwidth, the UltraSparc uses a hierarchy of decoupled buses. The memory bus is 128 bits wide and runs at full processor speed. This connects via buffer chips to a 128-bit system bus that runs at half, one-third, or one-fourth the core speed. At the slowest level, the SBus is used for I/O to low-cost peripherals.
Sun implements this scheme at the har
dware level by a crossbar switch chip, which is part of the support chip set. This chip can isolate the memory bus from the I/O bus so that instead of stalling during memory reads, the CPU continues writing to graphics or other I/O devices. The effect of this scheme is high overall bus utilization and sustainable 1.3-GBps throughput.
The UltraSparc-II uses the Visual Instruction Set (VIS), which includes 30 instructions for handling multimedia, graphics, imaging, and other integer-oriented algorithms. VIS instructions include addition, subtraction, and multiplication operations, which allow up to eight integer byte-wise or halfword-wise operations to be performed in parallel with a load or store operation and a branch in a single clock cycle.
This approach can be used to improve video performance. For example, for alpha blending (i.e., superimposing one image on top of another with a translucent top image), VIS includes instructions specifically designed to multiply the alpha value by the pixel va
lues, a process that can take many floating-point operations.
OFFICIAL INTRODUCTION DATE:
Second Quarter of 1996
CURRENT STATUS:
Design
LIKELIHOOD INTRODUCTION DATE WILL BE MET:
Excellent
TARGET CLOCK SPEED:
250 to 300 MHz
ESTIMATED PERFORMANCE:
350 to 420 SPECint92; 550 to 660 SPECfp92
FABRICATION PROCESS/FEATURE SIZE:
Five-layer-metal CMOS/0.3-micron
TECHNOLOGICAL ADVANTAGES:
The UltraSparc-II is a 64-bit, four-way superscalar CPU that Sun optimized for multimedia and networking applications rather than for outright CPU performance.
TECHNOLOGICAL DISADVANTAGES:
The lack of hardware assistance for instruction reordering places a premium on compiler quality and requires companies to recompile older software to reap the benefits of the UltraSparc's enhancements.
PRIMARY
MARKET:
Multimedia workstations.
WHERE TO FIND:
Sun Microsystems
Sunnyvale, CA
(800) 681-8845
(408) 774-8119
http://www.sun.com/sparc/Net.Engine
Sun UltraSparc-II
photo_link (37 Kbytes)
Sun Microsystems' UltraSparc offers nine execution units.
Sun Microsystems
