DOSSIER:
The PowerPC620 is the first 64-bit implementation of the PowerPC architecture. With 64-bit registers and internal data paths, and 7 million transistors, the 620 uses a larger die than -- and is almost twice as complex as -- the PowerPC 604. The 620 is a four-way superscalar design with six execution units: three integer ALUs, an FPU, a load/store unit, and a branch unit. The latter performs four-level branch prediction and speculative execution using a register-renaming scheme.
The microarchitecture of the 620's RISC core is similar to that of the 604. It differs mainly in its wider registers and data paths, and it has more reservation stations for speculative execution. Most o
f the overall performance enhancements come from a much-improved bus interface. There is now a 128-bit-wide memory interface that can fetch two 64-bit longwords per bus access and a 40-bit address bus that can address 1 TB of physical memory.
The bus interface offers integral support for a second-level cache of up to 128 MB, which can run at 100, 50, or 25 percent of the CPU's clock speed. This allows flexibility for the price of the memory parts used. The bus interface uses pipelined snoop responses, which reduce the latency due to bus snooping in SMP systems and improve throughput.
The 620 has the same 16-entry reorder buffer as the 604, which tracks instructions from dispatch to completion to facilitate out-of-order execution. However, the 620 releases up to four rename buffers per cycle (compared to the 604's two), making them more available to other instructions in the pipeline. As a result, the 620 needs only 16 rename buffers, compared to the 604's 20.
Nevertheless, the PowerPC's chal
lenge to Intel seems to have lost some of its momentum. The alliance's declared intention was to offer twice the price/performance value of a comparable Intel CPU. The 601 processor achieved this against the Pentium. Since then, however, Intel has been progressively narrowing the gap in terms of maximum integer performance. A 200-MHz 620 processor may appear in mid-1996, but a 200-MHz P6 will also arrive around then. While Motorola continues work on a fast 604+ chip, other RISC vendors, including Mips and HP, seem to be overtaking the PowerPC alliance in the absolute-performance stakes.
OFFICIAL INTRODUCTION DATE:
Fourth Quarter of 1995
CURRENT STATUS:
Sampling
LIKELIHOOD INTRODUCTION DATE WILL BE MET:
Good
TARGET CLOCK SPEED:
133 MHz
ESTIMATED PERFORMANCE:
225 SPECint92; 300 SPECfp92
FABRICATION PROCESS/FEATURE SIZE:
CMOS/0.5-
micron
TECHNOLOGICAL ADVANTAGES:
The 620 can software-switch between 64- and 32-bit modes. It can also switch between big-endian and little-endian modes; this will be useful for running mixed OSes, as is envisioned in IBM's future plans.
TECHNOLOGICAL DISADVANTAGES:
The performance of the 620 lags behind that of other next-generation RISCs.
PRIMARY MARKET:
Graphics workstations, SMP servers, parallel supercomputers, and Macintoshes.
WHERE TO FIND:
For Motorola information:
(800) 845-6686 or (512) 434-1502
http://www.mot.com.PowerPC/
or Motorola@Selectnet.BGA.com
For IBM information:
(800) 769-3772
620 Building Blocks
illustration_link (10 Kbytes)
The 620 is the PowerPC Alliance's first 64-bit processor. It software-switches between 64- and 32-bit modes.
PowerPC Alliance
