Tom R. Halfhill
What if almost everything that has been written about the PowerPC 615 is backward? What if IBM's goal is not to bring x86 compatibility to PowerPC systems, but rather to bring PowerPC compatibility to x86 systems?
The difference is subtle but crucial. It means IBM would have to design a PowerPC chip that works on standard PC motherboards and performs as well as the latest x86 processors. Yet, the same chip would also make its native instruction set visible to PowerPC-compatible OSes and applications. In other words, you'd get the same multiplatform compatibility that has been rumored all along for the 615, but within an ordinary PC instead of a system based on the PowerPC Ref
erence Platform (PReP), Common Hardware Reference Platform (CHRP), or Power Mac architectures.
Sources close to the project, but who spoke to us on the condition of anonymity, say IBM is developing exactly that kind of chip. Sources say this version of the PowerPC 615 will fit a Pentium socket on existing PC motherboards and deliver Pentium-level performance at a comparable price. It will also run native-PowerPC software at speeds competitive with other PowerPC processors.
This scenario raises a host of technical and marketing questions that only IBM can answer, and IBM isn't talking. However, by interviewing sources close to IBM, BYTE has pieced together an intriguing view of the PowerPC 615.
First of all, such a chip is technically feasible; similar x86 processors exist today. Intel's P6, AMD's K5, and NexGen's Nx586 all use a hybrid CISC/RISC design known as a decoupled microarchitecture. This design combines a RISC-like execution core with a sophisticated x86 instruction decoder. The dec
oder translates x86 CISC instructions into simpler RISC-like operations that execute more efficiently in a superscalar RISC core. It's a way of adopting the advantages of RISC while maintaining compatibility with x86 software.
Sources say that IBM is developing a similar chip that uses PowerPC as the RISC core. The chip also has an x86-style bus architecture and a Pentium pin-out, so it fits into Pentium sockets. However, unlike the P6, K5, and Nx586 -- which use RISC-like instructions for internal purposes only -- IBM's hybrid CPU can make both instruction sets visible to an OS.
One catch, according to sources, is that the hybrid chip can't easily switch between x86 and PowerPC modes. You have to boot up the system in one mode or the other to get full performance. Also, one source said the chip has a "fairly big die," which would make it relatively expensive to manufacture. But he said it's still cheaper than putting x86 and PowerPC processors in a system.
Another drawback is that a hybrid
CPU on a PC motherboard would need special versions of Windows NT and OS/2, apart from the existing PReP/CHRP versions. And it almost certainly wouldn't run the Mac OS, which supports the largest installed base of PowerPC software.
Nevertheless, if this variation of the 615 goes into production, it could be IBM's way of hedging its bets. The hybrid CPU could compete directly with the Pentium for sockets on PC motherboards, ensuring some kind of future for PowerPC chips in case PReP and CHRP fail. It would also let the PowerPC infiltrate the mainstream PC market.
IBM is believed to have several variations of the 615 in development. The first announcements are expected in the first half of 1996.
Pentium-Pin-Out PowerPC
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Based on information obtained from sources close to IBM, this speculative design for a Pentium-pin-out PowerPC chip shows how a PowerPC core could be united with an x86-compatible bus. The dual-mode CPU would support both instruction sets, routing x86 instructions through a special decoder that converted the CISC instructions into native-RISC instructions.
Tom R. Halfhill is a senior editor for BYTE in San Mateo, California.
Alternate Views of the 615
