A look at how tomorrow's next-generation chips stack up
Dick Pountain and Tom R. Halfhill
CPU choices used to be clean when the great rivals, CISC and RISC, were in two distinct camps. But with the CPU introductions set to begin late this year, each camp steals the other's best ideas, and blurs replace distinctions.
For example, Intel's P6 translates long x86 CISC instructions into simple, fixed-length micro-operations executed by what is essentially a RISC processor core. Sun Microsystems' UltraSparc-II will boast special graphics instructions to speed up the MPEG decoding that would require up to 48 instructions on other processors. These are CISC instructions in all but name.
The scorecards on the following pages show that next-generation CISC and RISC CPUs will fight performance battles on four fronts: execut
ing more instructions per cycle, executing instructions out of order to sidestep dependencies, renaming registers to avoid register famine, and contributing to faster overall system performance, not just CPU speed.
All these chips issue more than one instruction per cycle; the five RISC CPUs here are all four-issue superscalar designs. But they vary in the number of function units they provide, ranging from nine in the UltraSparc to four in the Alpha 21164.
Processes are shrinking, too. Intel, Digital, and Mips will all deliver 0.35-micron chips by early 1996. By 1997, expect to see CPUs built in 0.25-micron CMOS, clocked at 400 MHz, and delivering 1000 SPECfp95. It's also reasonable to expect that by then software designers will have found a way to soak up all that power and redraw the battle lines.
Dick Pountain is a BYTE contributing editor based in London. Tom R. Halfhill is a BYTE senior editor based in San Mateo, California. You can reach them on the Internet or BIX at
dickp@bix.com
and
thalfhill@bix.com
, respectively.
CPU Scorecards
