drome) lead HP's VLIW compiler effort. Trace scheduling and software pipelining, pioneered by Fisher and Rau, respectively, are now central pillars of VLIW compiler technology.
The trailblazing Multiflow 7/300 used two integer ALUs, two floating-point ALUs, and a branch unit (all built from multiple chips). Its 256-bit instruction word contained seven 32-bit operation codes. The integer units could each perform two operations per 130-ns cycle (i.e., four in all) for a performance of about 30 integer MIPS. You could also combine 7/300s to build 512- and 1024-bit-wide machines.
Cydrome's pioneering Cydra 5 also used a 256-bit instruction word, with a special mode that executed each instruction as a sequence of six 40-bit operations. Its compilers could therefore generate a mix of parallel and conventional sequential code.
While both those VLIW machines used multiple chips, some regard Intel's i860 as the first single-chip VLIW. It d
epends on the compiler rather than on the hardware to sequence operations correctly.
VLIW isn't solely for CPUs. Holland's Philips Semiconductors, another VLIW innovator, recently launched its VLIW TriMedia digital signal processor chip. TriMedia aims at high-end applications such as multimedia PCs, videoconferencing, TV set-top boxes, and digital video cameras. The goal is to be fast enough to eliminate the need for a host CPU and cheap enough at $50 to keep total system cost down. Such dedicated niche applications may keep VLIW on the charts.
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Short History of Long Instructions
