rform caller-ID verification and be able to display messages on an LCD screen. Combining these functions traditional-ly required adding two processors to a product's design.
Early this year, Motorola introduced
the DSP56800
, a 16-bit processor core designed to tackle low-cost designs that require DSP and microcontroller functions. Because these capabilities are combined into one chip, the DSP56800 core saves board real estate, minimizes power consumption, and reduces a design's parts count. It also trims RAM usage, because you don't have to store separate DSP and microcontroller programs.
The DSP56800 core offers a streamlined DSP instruction set derived from its 56000 DSP line. This allows existing 56000-based DSP applications written in assembly to run with little or no modification. It also provides a host of microcontroller functions, such as timers for fielding periodic events, serial peripheral interfaces that communicate with peripheral
s, and up to 32 general-purpose I/O (GPIO) signals that can monitor or control devices.
A phase-locked loop (PLL) enables the processor to operate at different clock speeds at different times, to either conserve power or boost performance. It's a fully static design that operates from DC (i.e., no clock) to 40 MHz. At this speed, it consumes only 27 milliwatts. This power-consumption level makes the processor ideal for PC Cards and mobile devices.
Combining the Odd Couple
It's hard to imagine merging two processors whose functions are so vastly different. A microcontroller, as its name indicates, controls devices. Microcontrollers normally don't need to be speed demons: The devices they manage usually require a response within milliseconds, or even several seconds.
On the other hand, a DSP's sole purpose in life is to rapidly process data. It executes sophisticated mathematical operations--such as a voice-compression/decompression algorithm--repetitively so that it can p
rocess signals in real time. To accomplish this, a DSP has a repertoire consisting of fast math instructions and matrix operations.
Motorola designed the DSP56800 core from the ground up. First, the designers profiled the instruction usage of many DSP and microcontroller applications. Seldom-used DSP56000 instructions were discarded first. Others instructions were eliminated if they complicated the processor architecture or weren't compact in size. The resulting instruction set offers a gamut of DSP capabilities, such as a fast multiply-accumulate (MAC) instruction and a fixed-point data type. For microcontrollers, there are instructions for bit manipulation and interrupt handling.
The end result was a streamlined instruction set that reduces a firmware program's size by one-third. According to Motorola, the DSP56800's code storage compares favorably to that of an 8-bit microcontroller, even though the core is a 16-bit processor. Due to the efficiencies of the instruction set and architecture, M
otorola says the DSP56800 delivers 20 MIPS at 40 MHz.
Processor Architecture
The DSP56800 core uses a Harvard
architecture
with separate address and data buses. The core is full of data and program buses that permit up to three simultaneous accesses to data and program memory; this expedites the movement of data and code throughout the processor. The core also has several concurrent execution units.
The data arithmetic logic unit (ALU) provides nonpipelined multiply and MAC operations. It also has a complement of arithmetic and logical operations; the latter help test the status of devices. A 16-bit bidirectional barrel shifter enables fast data-stream parsing (such as a network protocol stream), which reduces programming overhead.
The ALU also has two 36-bit accumulators and three 16-bit input registers. Arithmetic and bit results alike can be written back to any register, not just the accumulators; this simplifies programming and improves performa
nce.
The bus- and bit-manipulation unit handles many control activities, such as bit-manipulation operations and bit-test and bit-branch instructions. It complements some of the ALU's arithmetic and shifting operations.
As a separate unit, the address-generation unit (AGU) can pipeline instructions and compute the next address in advance. It can manage two data-memory accesses and two address updates in one instruction. It has a modulo addressing mode that's effective at implementing circular buffers for DSP applications.
The program controller (PC) manages the overall operation of the core. It fetches and decodes instructions and routes them to the appropriate execution unit. The PC supports the hardware and software stacks. A two-level hardware stack implements hardware DO and REP loops--the staple of DSP algorithms--for performance. These hardware loops have zero overhead yet are interruptible, which reduces interrupt latency.
The DSP56800 core has an on-chip expansion area that
sports additional on-chip memory and several types of integrated peripheral modules. There are two kinds of serial interface modules, a timer module, and a general-purpose I/O (GPIO) interface module. Certain modules, such as serial I/O, can be programmed to behave as GPIO modules.
Currently Motorola is sampling the DSP56800 core as two configurations with different resources in the expansion area. The first is the DSP56L811, which contains 2 KB of program RAM and 4 KB of data RAM; the second is the DSP56L812, which contains 44 KB of PROM, 4 KB of data ROM, and 4 KB of data RAM.
Given its wealth of DSP and controller functions, the DSP56800 is well suited for a variety of applications. For example, a DSP56L812 could not only operate as a data pump for a low-cost V.22bis fax/data modem but also handle all the modem-control signals, such as on/off hook and carrier detect. A high-density disk drive could use the DSP56L812 not only to operate the servos that steer the head mechanism but also to rea
d, process, and buffer the data. In addition, the DSP56800 has an advantage in projects where time to market is critical, because it can be programmed in C.
Technical Specifications
Physical
2.7-V part
0.65-micron three-metal-layer CMOS
100 pin TQFP, 14 square millimeters
Peripheral interface
16 dedicated GPIO pins (eight programmable as interrupts)
Two serial peripheral interfaces, configurable as two four-pin ports
or eight GPIO pins
One synchronous serial interface, configurable as a six-pin port or
six GPIO pins
Three programmable timers with two I/O pins, configurable as two
GPIO pins
illustration_link (14 Kbytes)
How the DSP56800 processes a DSP instruction.
illustration_link (15 Kbytes)
How the DSP56800 processes a microcontroller instruction.
Tom Thompson is a BYTE senior technical editor at large. You can reach him at
tom_thompson@bix.com
.
Two, Two Chips in One!
