cells on the chip to replace failed ones. In addition, most flash-memory systems for data storage use a technique called leveling, which amounts to moving the data around on the chip to "wear" each cell as equally as possible.
Another consideration is that erasing a cell of flash memory takes much longer than erasing a bit of data on a hard drive. Like hard drives, flash-memory systems typically erase files by erasing entries in the memory table rather than erasing all the data. Inevitably, however, they will need that space again, and they must write over the data in those sectors. This is a more time-consuming process than it is with a hard drive.
Anatomy of a Flash
A flash-memory cell is like a conventional transistor with an extra gate. (The scheme shown in the figure
"Two Competitors: NAND Flash...NOR Flash"
is Intel's ETOX IV NOR flash, but most of the others are similar.) Between the source and drain and the control gate,
there is a second gate, called a floating gate, that serves as a charge storage mechanism (
see the figure
). Thin layers of oxide isolate the floating gate from everything else.
When a sufficiently large voltage goes across the source (at ground potential; see "Source n+"
in the figure
) and the control gate (at programming voltage), electrons (depicted by "-" in the figure) tunnel through the oxide layer and accumulate in the floating gate. This process is called
channel hot electron injection
. The extra negative charge (electrons) in the floating gate raises the cell's turn-on threshold by increasing the negative potential opposing voltage. That writes a
zero
in the cell, instead of the one of the erased (uncharged) cell.
Erasing the cell reverses the process. Grounding the control gate, and bringing the source to programming voltage, removes electrons from the floating gate and reducing the turn-on threshold. That turns the cell bac
k to a
one
.
Oddly, erasing does not happen "as quick as a flash": It takes a long time. The reason is that the relatively high voltage involved (at least 10 V in most schemes) entails a good deal of current. Since there are limits to how much current chips can handle, there are limits to the number of cells that can erase at once, too. That's why erasing occurs one group of cells at a time.
The basic technology lends itself to flashy variations. Most of them involve a floating gate. For example, AMD uses a variation that erases by putting a positive voltage on the source and applying a negative voltage to the drain. National Semiconductor's technology erases by floating the source and drain, holding the control gate at 0 V, and applying a 20-V potential to the substrate.
Pressing the Flash
Flash memory is still new enough that there is no one way to make it. Manufacturers take about a dozen different approaches to making and organizing flash-memory cells on a sl
ab of silicon. Some are better for data storage and some for code storage (storing the BIOS on a motherboard, or firmware on disk drives and modems).
Ironically, the common method of referring to flash technologies--by the logic scheme they use--is mostly not a function of the technology at all, but the way the manufacturer chooses to arrange the cells. You're not absolutely free to substitute cell arrangements using different cell technologies, but pretty much so.
NOR (
see the figure
) is the leading technology today, and Intel is the major manufacturer. It organizes the memory cells in parallel fashion, with each cell's drain connected to a bit line, and many bit lines are grouped to make up an I/O group. The select line connects the control gates of a row of cells, one on each bit line. With this layout, it can access several cells, such as a byte or a word, in parallel. NOR provides faster random access, but its parallel structure reduces memory density.
NAND (
see the figure
) is a technology used by National Semiconductor, Samsung, and others. It connects the cells serially, with a select gate for every few control gates (usually, one select gate per byte or word) and serial connections to the control gates in that group of gates. NAND has slower random access, but it allows higher densities due to its smaller-size cells.
illustration_link (8 Kbytes)
NAND memory connects cells serially, for higher densities. NOR cells are in parallel, for faster access.
illustration_link (6 Kbytes)
Left:
Electrons accumulate in the floating gate: a zero.
Right:
Electrons leave the floating gate: a one.
How Flash Memory Works
