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ArticlesRISC and DSP in One Architecture


September 1996 / International Bits / RISC and DSP in One Architecture
Bob Emmerson

As multimedia and data communications applications become more sophisticated, they demand fast RISC processors and high-quality digital signal processors (DSPs). Conventional designs hav e either separate modules or integrate RISC and DSP on the same chip but in separate cores.

The 50-MHz Hyperstone E1-32 microprocessor, from Hyperstone Electronics (Konstanz, Germany), was introduced early this year. It takes another route by incorporating a RISC unit that is capable of performing DSP algorithms. The DSP instruction set can work in parallel with the system's ALU. The result is higher flexibility because during latency cycles of the DSP, the ALU can execute other instructions. Additionally, the DSP unit be comes more robust because it can use all resources (cache, internal memory, I/O, and bus interface) of the RISC processor.

New systems, such as Hypercope's ISDN PC Card, that deploy the Hyperstone E1-32 microprocessor are starting to appear. They capitalize on the microprocessor's autonomous handling of communications, compression, and encryption protocols in a single compact unit.


Hyperstone's RISC Board

photo_link (13 Kbytes)

Hyperstone's RISC-DSP E1-32.


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Flexible C++
Matthew Wilson
My approach to software engineering is far more pragmatic than it is theoretical--and no language better exemplifies this than C++.

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