Multimedia Instructions: The CPU Acts Like a DSP

Sun Microsystems was the first company to introduce CPU multimedia features, with its Visual Instruction Set (VIS) for its UltraSparc CPU. Now all major processor architectures (except PowerPC) have defined multimedia instruction extensions, which vary somewhat in scope and feature sets. These instructions accelerate calculations and make most 2-D and 3-D graphics and/or video, audio, voice-processing, and data communications tasks up to several times faster.

So-called multimedia extensions are actually instructions that deal with arithmetic and logic operations. These are done on packed data types, such as 8- by 8-bit bytes, 4- by 16-bit words, or 2- by 32-bit doublewords, all packed inside one 64-bit quadword.

Integrated Processing

Based on the single instruction/multiple data (SIMD) principle, multimedia extensions can process multiple sets of small operands and obtain multiple results with a single instruction. Operations include packing and unpacking, arithmetic, comparisons, logic, shifting, and (on SPARC and Alpha machines) motion estimation for motion-video encoding. The ultimate goal is the integrated real-time processing of multiple audio, video, and 2-D and 3-D graphics streams on a system CPU, although time is still needed to attain that level of performance.

Several multimedia extensions have been announced thus far: Matrix Manipulation Extensions (MMX) for the Intel x86, VIS for SPARC chips, Motion Video Instructions (MVI) for Alpha processors, and Mips Digital Me-dia Extensions (MDMX) for Mips processors. Intel's MMX focuses on augme nting the old, outdated x86 architecture so that it can handle basic multimedia. VIS, MVI, and MDMX build on more-solid RISC architectures with three-operand instructions and large sets of 64-bit registers (which are already present) to facilitate multimedia tasks.

On Intel's P55C and Klamath chips, the ALUs and eight 64-bit media registers are shared with the FPU, so MMX and floating-point instructions cannot be processed simultaneously. This is a problem during rendering operations, where the FPU is doing geometry calculation and MMX instructions are simultaneously trying to do texture mapping. Frequent switching between floating-point and MMX modes can impair performance.

With the Alpha, on the other hand, the 32 64-bit integer registers handle multimedia operations simultaneously with other integer instructions. Sun's VIS is similar to Digital Equipment's MVI in that it enables operation on an entire 4-by-4 matrix directly to its 32 registers, compared to only eight registers for Intel's MMX.

MMX2

Intel's current MMX is primarily focused on image, audio, and video processing. Intel is expected to introduce in the first half of 1998 the MMX2 set of instructions for the planned Katmai Pentium Pro processor. The 0.25-micron-line-width Katmai, running at up to 400 MHz, should have a 2- by 32-KB cache and offer faster floating-point performance than its MMX-only, 2- by 16-KB-cache sibling, Deschutes.

How? Because the MMX2 will focus on floating-point-intensive 3-D graphics acceleration, and thus have much heavier memory demands. In fact, MMX2 is expected to have extensions that are very similar to the new MDMX extensions for future Silicon Graphics Mips processors.