Inspecting Chip Wafers

June 1997 / International Features / Get the Right Picture / Inspecting Chip Wafers

The inspection of defects on chip wafers is one of the most challenging tasks in image processing. It requires the matching of scanned images with reference images in real time. This type of application needs data throughput rates o f up to 80 million pixels per second and about 15 billion operations per second (BOPS) to detect defect locations.
After image acquisition on standard frame-grabber boards, Parsytec CC/ipp machines separate images into fractions and stream these subimages to the multimedia processors at different nodes. A software master process controls the distribution of these image fractions. At each node, one or two multimedia processors a nalyze the image parts as they arrive (at speeds of more than 28 MBps) and reveal regions of interest that may include defects by comparing them to reference descriptions.
Standard Pentium Pro processors then register regions of interest and flag defects to the master process. The defective wafers are eliminated from the line.

Finding Defective Wafers
illustration_link (28 Kbytes)

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Matthew Wilson
My approach to software engineering is far more pragmatic than it is theoretical--and no language better exemplifies this than C++.

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