es can price these systems competitively. Finally, low power consumption to extend battery life and reduce the overall operating cost is a primary concern.
A Tour of the SH-3
Hitachi developed the SH-3, its latest 32-bit RISC processor, to address the demanding requirements of emerging products such as hand-held PCs (HPCs). The company based the SH-3 on its SuperH RISC architecture, which has a large, uniform logical address space and a high-level-language orientation. The SH-3 is a pipelined implementation of the SuperH architecture with a large on-board cache, memory management unit (MMU), and software-programmable power management functions.
The first two members of the SH-3 family, the SH7702 and the SH7708, are housed in a 120-pin Plastic Quad Flat Pack
age (PQFP) and 144-pin PQFP, respectively. Both processors are fabricated using 0.5-micron CMOS technology. Because the CPU core size consists of less than 6mm
2
of the overall 43mm
2
die size, the rest of the die is used for on-chip memory and peripheral support, as shown in the figure
"The SH-3 Microarchitecture"
.
At the heart of the SH-3 is the SuperH RISC engine. It has a five-stage pipeline with a hardware multiplier, 32-bit internal data paths, and 25 32-bit registers (i.e., 16 general-purpose registers, five control registers, and four system registers). The SH-3's engine manages a 4-GB, byte-addressable, unsegmented physical address space.
A 16-bit fixed instruction length offers significant code efficiency over 32-bit fixed-instruction-length processors of 40 percent to 60 percent, and 60 percent compared to conventional variable-instruction-length processors. An execution rate of one instruction per cycle, combined with fast clock speeds of 60 MH
z (100 MHz in future releases), lets programs run quickly and efficiently.
A primary determinant of overall processor performance is the size of the on-board cache. The SH7708 integrates a full 8-KB four-way set-associative cache. An MMU with a resident 128-entry translation look-aside buffer (TLB) handles the efficient management of on- and off-chip memory and reduces power consumption. The MMU uses Address Space Identifiers (ASIDs) that implement memory protection during multitasking with multiple virtual memory modes. Thus, each process has its own virtual memory and is prevented from accessing the resources of another process or the OS kernel. To manage the varying requirements of complex OSes, the MMU's address translator uses a paging system that supports either 1- or 4-KB page sizes for efficient main-memory management.
The SH-3 also features a Bus State Controller (BSC). The BSC allows direct connection with various external memory components such as DRAM, static RAM (SRAM), synchronous DR
AM (SDRAM), pseudostatic RAM (PSRAM), and ROM to minimize external logic and cost. The 32-bit external bus consists of 26 address lines and seven predecoded chip selects. These are configurable, so that the SH-3 can use the appropriate clock speed (i.e., one-fourth, one-half, or system clock speed) for the type of memory accessed, on an area-by-area basis in the physical address space. You can also specify bus wait states. The 32-bit width of the bus provides enhanced performance over narrower 16-bit configurations, although the designer can configure the bus for 16-bit operations.
The SH-3 offers support for a large number of on-board peripherals with a 32-bit three-channel timer, a real-time clock (RTC), an integer multiplier-accumulator, a barrel shifter, a user break controller for on-chip debugging, and serial communications with a smartcard interface, per the ISO 7816-3 specification. The SH-3 also directly supports a PC Card controller interface. This lets the SH-3 manage up to two Type II PC Car
d slots.
To address low power consumption, even during high-speed operation, the SH-3 features some built-in power management functions. The first category of such functions is software-controlled power management. Three power-reduction modes -- sleep, standby, and module standby -- are supported. In sleep mode, the CPU core stops operating while other functions remain active. In standby mode, an RTC maintains key system data while the CPU core and peripherals are powered off, enabling current consumption of less than 4 microamperes (or 1 µA if you don't use the RTC). In module standby mode, the CPU remains active while idle peripheral modules are disabled until needed.
Because the cache and TLB account for about one-third of total power dissipation, the SH-3 also deploys three hardware power management schemes aimed at reducing cache power dissipation. The first scheme has only one of four cache data arrays powered when the operating frequency is sufficiently low for sequential operation (l
ess than 40 MHz). Above this frequency, the four data arrays operate in parallel.
The second scheme, termed the pulse-word technique, restricts the voltage swing of the word line so that it is narrower than a full V
CC
-to-ground swing, but wide enough for correct sense-amplifier operation.
The third scheme is called the isolated bit-line technique. In it, column switches are placed on bit lines between memory cells and latch-type sense amplifiers. These column switches reduce sense-amplifier loads by isolating parasitic capacitance of the bit lines from the active sense amplifiers.
Glove-Fit for HPC
The capabilities of the SH-3 map particularly well into HPC applications. For cost-sensitive and power-sensitive HPC applications, the 100-MIPS (Dhrystone benchmark) performance of the SH-3 makes it a practical solution. The SH-3's 32-bit architecture with 16-bit fixed instruction set efficiently supports advanced applications and complex data types required by HPC users. Hita
chi designed the MMU functions, such as variable page size, ASID support, and cache size, to ensure optimum operation of leading OSes such as Windows CE.
The advanced power management capabilities of the SH-3 provide for very low power dissipation. At 100 MHz, the SH-3 dissipates 700 milliwatts. The SH-3's broad spectrum of on-board peripheral support (as shown in the figure
"A Sample HPC System"
) facilitates a small HPC system size, reduced parts count and cost, and low power consumption. The large volume of processors that Hitachi produces makes it possible to price the SH-3 below $25 per unit, in lots of 1000.
The suitability of the SH-3 processor for HPC applications is evidenced by the fact that it was designed into five of the seven Windows CE HPCs that were announced at Comdex last year, as well as several traditional HPCs and high-end PDAs, such as Sharp's Color Zaurus. With its on-chip MMU, extensive peripheral integration, and power-conservative design, the SH-3 pro
vides powerful enabling technology for emerging personal-access products.
illustration_link (36 Kbytes)
The SH-3 processor has a powerful RISC core, virtual memory support, and ample I/O interfaces.
illustration_link (37 Kbytes)
The SH-3, co
mbined with a companion ASIC, provides a glueless interface to many HPC system functions.
Lyle Supp is a product marketing manager for RISC MPUs/MCUs at Hitachi America, Ltd., Semiconductor and IC Division. You can contact him at
lyle.supp@halsp.hitachi.com
.
The Heart of Hand-Held PCs
