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ArticlesThe K6 Alternative


July 1997 / BYTE Hardware Lab Report / The K6 Alternative

Intel invented, innovated, and has controlled the evolution of x86 chips from the 8088 to the Pentium Pro. There were a few blips on the radar, but generally other chip manufacturers have been relegated to carrying the train on Intel's gown.

With the Pentium Pro, however, optimized for 32-bit operations at the expense of 16-bit operations, Intel had outrun the installed base of OS and applications software. As long as the Pentium remained the chip of choice, a dangerous window of op portunity opened for other chips. To distinguish its products again, Intel created the multimedia extensions (MMX) Pentium.

The AMD K6-MMX, however, changes the PC landsc ape considerably. Introduced at the right time with ample power and a competitive price, the K6 might offer the first serious challenge to Intel's dominance.

Under the Hood

The K6 matches the Pentium Pro's excellent 32-bit performance without the Pentium Pro's characteristic slowdowns running 16-bit software. AMD uses a 0.35-micron, five-layer-metal process to manufacture the 8.8-million-transistor K6. This chip features the industry's largest L1 caches: a 32-KB data cache and a 32-KB instruction cache -- twice those of the MMX Pentium. The K6 is currently available at clock speeds of 166, 200, and 233 MHz, and 266- and 300-MHz versions are expected soon.

The K6 uses a six-issue RISC86 superscalar microarchitecture that's significantly different from that of the Pentium or Pentium Pro. The K6 microarchitecture decodes x86 instructions into simpler, fixed-length RISC86 op codes.

Some RISC techniques used in the K6 include multiple instruction decode, single-clock execution, out-of-or der execution, data forwarding, speculative execution, and register renaming. In addition, the K6 implements an 8192-entry branch history table, a branch target cache, and a return address stack, which deliver a prediction rate greater than 95 percent. The K6 also contains seven execution units that enable superscalar operation in a six-stage pipeline.

Form and Function

Intel's dominance lets it dictate standards -- witness its current attempt to move the industry toward plug-in CPU cards. AMD knows that it cannot demand change. Thus, the company went out of its way to ensure compatibility with existing packaging and system-interface standards.

The K6 uses a Socket 7-compatible, 321-pin ceramic pin grid array. OEMs can adapt current designs to fit the K6 without the R&D costs required for a new platform. The K6 itself is slightly less expensive than other sixth-generation processors, due in part to its compact die size.

Current K6 systems aren't perfect. Some vendors report disa ppointing video performance. Their testing indicates that existing chip sets and BIOSes, optimized for the older Pentium but not the MMX Pentium or Pentium II, may be holding back the K6 from its full performance. Nonetheless, as these problems are eliminated, the K6 will be a potent competitor to the Intel CPUs.


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Flexible C++
Matthew Wilson
My approach to software engineering is far more pragmatic than it is theoretical--and no language better exemplifies this than C++.

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