AMD's K6 Road Map

AMD plans two new versions of the K6 for 1998. The first chip, scheduled for the first quarter, will have the AMD-3D extensions, system bus frequencies as high as 100 MHz, a superscalar MMX unit, and 0.25-micron process technology.

The faster bus will match Intel's frontside bus on the Pentium II, which wil l run at 100 MHz when Intel introduces the 440BX system chip set next year. Equally significant is the K6's new MMX unit. Current K6 processors can execute only one MMX instruction per clock, while Inte l's chips can execute two per clock. In an attempt to match Intel's multimedia performance, the new K6 will have a dual-pipelined MMX unit.

Currently, the K6's top core speed is 233 MHz. That should soar to 300 MHz and higher as AMD rolls out the more efficient 0.25-micron process at Fab 25 in Austin, Texas.

In the third quarter, AMD plans to release another K6 that has the previously mentioned features plus a 256-KB Level 2 (L2) cache integrated with the CPU core. The L2 cache will run at the full core frequency over a dedicated backside bus, similar to the Pentium Pro's.

However, the K6's L2 cache will be truly integrated with the CPU. The Pentium Pro's L2 cache is on a separate die in a multichip module. A new Pentium II processor scheduled for introduction in mid-1998, code-named Deschutes, will also have a full-speed L2 cache, but the cache will be on separate static RAM (SRAM) chips inside the Pentium II's Single Edge Contact (SEC) cartridge.