Centaur's WinChip Road Map

Centaur plans to deliver its 3-D graphics extensions in a new version of the IDT WinChip C6 next March or April. This adheres to Centaur's goal of introducing new chips about every six months. It's an aggressive schedule, but Centaur says the WinChip's relatively simple design makes it easier to revise, test, and manufacture. (See "Keeping It Simple," October BYTE.)

The new chip, code-named C3A, will have several additional improvements. A new superscalar MMX unit will have dual pipelines and will execute some instructions in fewer clocks than Intel's Pentium chips. For example, Centaur's MMX multiply instruction wi ll have a latency of one clock instead of three. Centaur claims the C3A will run Intel's Media Benchmark faster than a Pentium.

To address another shortcoming, the C3A will offer twice as much FP performance as the C6. Centaur claims the C3A will match or exceed the performance of a Pentium on 80 percent of FP operations. Integer multiplication will be faster, too, and the chip will have branch prediction. Also, the data cache will be four-way addressable instead of two-way.

Although Centaur is sticking with a 0.35-micron process, the company hopes to push clock speeds a little higher, perhaps to 266 MHz. Remarkably, all these improvemen ts will add almost nothing to the chip's die size. It will expand to a mere 90 square millimeters, up from 88 square millimeters now.

Later in 1998, Centaur plans to release a WinChip series processor with an integrated Level 2 cache. That should significantly boost the chip's performance and help keep Socket 7 a viable alternative to Intel's CPU slots.