Synchronous DRAM provides burst rates of up to 150 MHz, significantly higher than the standard 60-ns, 40-MHz extended data out (EDO) DRAM in today's systems. SDRAMs with 64-Mb capacity are already shipping. Most of SDRAM's ini
tial incompatibilities with Intel's strict timing specs for the i440LX (66-MHz bus) and i440BX (100-MHz bus) chip sets have been ironed out.
ESDRAM
Enhanced SDRAM is the latest in a string of enhanced memories developed by Ramtron, which focuses on chips with low latency and high sustained bandwidth.
DDR-SDRAM
To improve the per-pin bandwidth, you can transfer data on both edges of each clock. This technology is called double data rate (DDR). Most new memory architectures will use this capability. DDR-SDRAM, which is also known as SDRAM II, was finally approved as an official standard after vendor disagreements over data strobe and other design issues.
Direct RDRAM
Some six years ago, a small California start-up, Rambus, shocked the memory community with its
Rambus DRAM
. RDRAM offered 500-MHz memory bus throughput by using 8-bit buses with 250-MHz clocks and dual-data transfers using both clock edges, all with a pin count one-third of comparab
le DRAM. You could even upgrade the memory in steps of one chip, offering unprecedented granularity. Rambus and Intel now have the specification for the next-generation Direct Rambus DRAM, which Intel hopes to use in its Willamette- and Merced-based systems in late 1999.
SLDRAM
Designed by the SyncLink consortium of major DRAM manufacturers, SLDRAM is a new royalty-free, open memory standard. In
some ways similar to Direct RDRAM, SLDRAM implements a command-driven, packet-oriented, 16-bit, 200-MHz dual-data bus with 400-MHz throughput (800-MBps bandwidth). Like Direct RDRAM, SLDRAM lowers memory-bus pin count by using a fast, narrow data path. Fewer signals means easier control of electromagnetic interference and skew, as well as simplified board routing.
CDRAM
Mitsubishi's cache DRAM, which is offered in 4-Mbit and 16-Mbit chips, uses a small amount of on-chip cache (16 Kb) together with a very wide 128-bit internal data bus to achieve both a very high burst rate of up to 10
0 MHz and a very short pipelined access time of 7 ns. Its SRAM and DRAM banks operate concurrently.
Where to Find
Rambus
Mountain View, CA
Phone: 415-903-3800
Internet:
http://www.rambus.com