Intel's IA-64 Architecture

Today's departmental and enterprise servers are mostly based on RISC technologies developed by Hewlett-Packard, IBM Microelectronics, and Sun Microelectronics. With a total of between six and eight execution units on a chip, RISC processors offer superior performance. This speedy performance enables the development of solutions such as multiple integer-execution pipes, multiple floating-point pipes, and separate load/store and branch hardware.

In contrast, Intel is forging an innovative path toward explicit parallelism with its new IA-64 architecture, which relies on a new kind of cooperation between hardware and compiler. IA-64's most notable characteristic is its massive complement of registers: There are 128 integer, 128 floating-point, and 64 new speculative registers for the compiler to work with. This aids performance by obviating the need for the compiler to perform bulky register-renaming tasks.

Another important feature of IA-64 is its very long instruction word (VLIW) architecture. A packed instruction word, which is 128 bits wide, incorporates three separate instructions and maps them to functional units in the target processor. A template field specifies dependencies between the instructions and other packed words.

Intel's next-generation 64-bit Merced processor is part of the IA-64 line developed by Intel and technology partner HP. As a hybrid of Intel's x86 technology and HP's PA-RIS C chip, Merced will combine the benefits of RISC and CISC to offer Explicitly Parallel Instruction Computing (EPIC). With EPIC, instead of generating machine instructions sequentially and then letting the processor decide how to execute them, the compiler produces code already written in parallel. The parallelized instructions allow the chip to process a number of instructions simultaneously, theoretically making IA-64 chips more efficient.

The 64-bit chips, due in 1999, will also read the 32-bit code that's used by the current generation of Intel processors, which will make them backward compatible. That promises far better 32-bit performance than can be obtained using the alternative, software translation.