is definitely where European firms can compete best," say
s Mike Muller, VP of product marketing at ARM.
Several of the European Commission's ESPRIT projects focus on development of embedded processors and the software to go with them. The current emphasis is on digital signal processors (DSPs), multimedia encoders, and new design methodologies for application-specific integrated circuits (ASICs).
Hyperstone Combines RISC and DSP
One of the big challenges in microprocessor design for embedded applications is the combination of RISC and DSP functionality in the same processor core. Both functions are extremely important in devices such as smart phones, PDAs, set-top boxes, and laser printers. "Chips for these applications require both a RISC chip's excellent computing performance and a DSP's superior communications functions," says Dr. Matthias Steck, marketing director of the German chip designer Hyperstone Electronics.
A few approaches have tried to combine both designs on the same chip, but they tended to keep them as s
eparate function units -- communicating via an on-chip bus -- and so resulted in very large die sizes. However, the Hyperstone processor (sponsored by the OMI's EURICO project) combines a 32-bit RISC engine and a DSP in the same core. The
Hyperstone architecture
lets both DSP and RISC units share key resources like cache, on-chip SRAM, I/O unit, and bus interface. This approach not only brings down costs by avoiding duplication of resources, it also makes the programmers' task much easier, as they no longer need to worry about synchronizing CPU and DSP operations -- both are part of the same instruction set. Hyperstone's CPU and DSP cores also share the same address space, which further removes the need to transfer data between the units using DMA (as in conventional twin-chip solutions).
Both engines can work in parallel, executing, for example, a fast multiply-accumulate or a complex multiply DSP operation at the same time as a load/store or address calculation in the RISC engine
. The DSP engine also shares the register set with the RISC engine, operating in parallel with the RISC's arithmetic logic unit, which can execute non-DSP instructions during the latency cycles of DSP instructions.
Applying RISC design principles like pipelining to the DSP engine means the DSP can run at clock speeds of over 100 MHz. Conventional stand-alone DSPs have mostly been stuck below 40 MHz. In return, the availability of complex DSP operations allows Hyperstone to use variable-length instructions that yield far better code density than pure RISC processors. Hyperstone instructions typically occupy half the memory of equivalent RISC code, which reduces the need for expensive memory.
Low-Power Chip
Two implementations of the Hyperstone architecture -- the E1-32 and the E1-16 -- have been deployed in several applications. These versions differ only in their external bus architecture.
A Korean licensee, LG Semicon, now also manufactures and markets the E1-32 and uses it in its
ASIC designs. LG's latest silicon is an E1-32 fabricated in 0.6-micron CMOS, which offers performance of 66 MIPS at 66 MHz and 5 volts. Running at full speed, the 66-MHz E1-32 still consumes less than 1 watt of power, which means Hyperstone has crossed the economically important 200-MIPS/watt threshold for low-power chips. LG also manufactures the chip in a 50-MHz version at 3.3 V. Later this year, it will start producing 0.35-micron versions running at more than 100 MHz.
Performance of the processor family has almost doubled from the E1-32's 66 MIPS to 120 MIPS, accomplished with the latest version, the E1-32XP. The next generation of the Hyperstone architecture, E2, which is expected to be available in silicon late in 1998, will feature significant improvements in the DSP instruction set and have 8 KB of on-board RAM.
These continuous functional improvements go along with an increase in performance. Says Hyperstone's Steck, "In 18 months we will see another performance boost to 180 MIPS [in the
E3 design]." The E3, slated for mid-1999, will feature better multimedia instructions and chip circuitry down to 0.25 microns.
EURICO Supports Hyperstone
The EURICO consortium is also working on a complete software environment for deploying Hyperstone, including real-time operating systems, C compilers, and other low-level development tools. The Belgian company Eonic Systems, for example, is porting its Virtuoso Nano OS kernel to Hyperstone, while Italy's Etnoteam is working on a full port of its Architecture-Neutral Distribution Format (ANDF) implementation to simplify Hyperstone's use in multiprocessor environments. (ANDF is a cross-platform binary software standard that allows applications to run on multiple platforms via on-the-fly translation.)
Other EURICO team members have developed several products based on the Hyperstone architecture. The German company SysKonnect, for example, designed a prototype of an Ethernet-to-ATM switch, and France's I&T COM built a low-cost cable mo
dem. On the software side, Visual Tools, in Spain, is working on a software library of components for video and image compression. The Universität der Bundeswehr, in Hamburg, assists these projects by creating timing simulators to evaluate the performance of Hyperstone-based applications.
Components Are Crucial
While sponsoring primary research certainly helps morale in the European semiconductor industry, it's only a start. To successfully turn processors such as Hyperstone into an industry platform, broad access to components that integrate with the platform is mandatory.
Development and design of components is the rationale behind ESPRIT's Europractice project. (The
practice
part of the name stands for PRomoting Access to Components, subsystems, and microsystems Technologies for Industrial Competitiveness in Europe.) Europractice complements OMI by encouraging joint research and industry projects to apply state-of-the-art chip technology in prospering markets. Europractic
e concentrates on ASIC design methodologies, multichip modules, and microsystems (complete devices like gas analyzers or radio transponders hosted on a single chip).
Europractice participating institutions include IMEC, in Leuven, Belgium; ETH Zurich; Fraunhofer Institute, in Stuttgart; the Rutherford Laboratory, in Oxford; and NMRC, in Cork, Ireland. Industrial partners include GEC-Marconi, SAGEM, Bosch, and Smith Engineering.
Belgium's IMEC, Europe's largest independent semiconductor research and development center, plays a significant role in Europractice's ASIC research. IMEC specializes in semiconductor processing and design methodologies. It owns 3300 square meters of clean-room space and has over $60 million in annual turnover from agreements and contracts with government agencies, aerospace firms, and semiconductor companies. Industrial clients include multinationals like TI, Philips, Intel, and Motorola. The institute's projects span the whole range of semiconductor research: basic work o
n submicron fabrication technologies, opto-electronics, materials science, memory technologies, solar cells, communications products, and futuristic research on quantum devices and epitaxial silicon heterostructures.
It also has considerable experience in chip manufacturing. IMEC's new CAST service, for example, provides universities and industrial firms with small quantities of prototype chips.
Codesigning ASICs
One of IMEC's most interesting current projects investigates new design methodologies for ASICs. Today, ASICs are usually built from off-the-shelf macro-cell circuits such as RISC or DSP cores and customized circuitry to meet the needs of specific applications. This reduces design and debugging time to a certain extent because the core has already been tested in the field.
However, as the industry is now passing beyond 0.35-micron process geometries, it's possible to build whole systems on a single chip, with one or more major functional cores, RAM, ROM, and custom processi
ng circuitry. The aim of IMEC's newly developed design methodology is to devote custom hardware to the hardest parts of the job, while processing the less critical parts in software running on a RISC or DSP core.
A team of application experts, hardware engineers, and software developers usually conceives the design of such chips and the corresponding firmware. IMEC, therefore, developed a suite of tools that supports the cooperative and simultaneous design -- codesign -- of an embedded system's hardware and software. "Our tools support interactive system design and automate the most error-prone design steps," says IMEC's Ivo Bolsens.
Codesign involves
first creating a specification for the embedded application, using an abstract notation in which processes communicate by remote procedure calls. The next step is to partition this specification by assigning the more critical processes to custom hardware blocks and the others to software running on CPU or DSP cores. Developers t
hen go on describing the hardware blocks using their usual circuit design tools and generating the software processes in C or C++ code.
At this point IMEC's automated co-design tools, called CoWare, jump in and automatically generate all interfaces that will bind these hardware blocks together. CoWare generates interface cells, handshake protocols, and processor I/O blocks while at the same time building the corresponding I/O drivers and real-time kernel functions to schedule the processes.
IMEC's recent spin-off company, also called CoWare, now further develops and markets the CoWare tool suite. The current product includes an interface generator, called Symphony; a retargetable code generator, called Chess, that simplifies software design; a retargetable simulator (Checker); a specifications converter (Matisse); and a decision-support tool for designers (Atomium).
Chess can compile the same C source program into machine code for a variety of different RISC cores, based on parameterized tem
plates. Checkers assists in designing custom DSP cores by simulating their instruction sets at thousands of instructions per second. Matisse, still in prototype stage, turns a high-level specification of a whole system into a CoWare description. From this description Symphony can then generate the corresponding interfaces.
Trade-Offs
When designing a DSP-based ASIC, many choices are possible between buffering data in memory or computing results on the fly and sending them over the circuitry. The choices adopted will affect power consumption as well as size and complexity of the final design. At present, most decisions on where to store and where to compute and send data is based on the designer's intuition, because usually there isn't enough time to try out all alternatives. Atomium, on the other hand, lets the designer experiment with different trade-offs between storage and communication channels to optimize physical properties of a chip.
Tools like the CoWare suite and the art of codes
igning ASICs could become very popular among semiconductor vendors. The reason is simple: Short design cycles and low power consumption are crucial features in all embedded applications.
Where to Find
CoWare
Leuven, Belgium
Phone: +32 16 298 440
Fax: +32 16 298 319
E-mail: marketing@CoWare.com
Internet: http://www.coware.be
European ASIC Designs
