Implementing an openIP Encryption Flow

By Andrew Dauman

July 17, 2006

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Today's extremely large and complex ASIC and FPGA designs use significant amounts of third-party intellectual property, in the form of general-purpose processor cores, digital signal processor cores, memory controllers, communications functions and so on. Furthermore, this third-party IP, which may account for a large proportion of the overall design, often originates from a number of IP vendors.

Due to the fact that each IP block represents a considerable amount of time and investment, it's no surprise that the IP vendors wish to guard their secrets. The way to do so is to encrypt the source. The problem is that right now there is no standard for encryption and decryption in electronic design flows that facilitates industrywide interoperability. Different IP vendors and

EDA vendors have used a variety of proprietary schemes, resulting in a huge support burden on the various organizations. Also, this practice is confusing to the end user and can result in a lack of consistency (simulating one version of the IP block and synthesizing a different version, for example).

To address this issue, the scientists and engineers at Synplicity have invented and implemented an open IP encryption environment that will facilitate the use of protected IP throughout the design flow: from IP vendor to EDA vendor to silicon vendor.

The advantages of Synplicity's proposed hybrid symmetric/asymmetric encryption/decryption technique are manifold. For starters, the IP vendor need create only a single version of the encrypted data, which is supplied to all interested parties. This ensures consistency, because it guarantees that the same IP will be used by all of the downstream tools. Moreover, fast symmetric encryption can be used for the large data blocks, while slower, more compute-intensive asymmetric algorithms are applied only to the small data keys.

But the key advantages to this scheme are that it is open, it leverages existing technologies and it fully addresses the needs of modern electronic-design environments.

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