Camera Modules, Image Sensor Wafer-level Packaging, and Silicon Layout

By Giles Humpston, Michael Nystrom

January 8, 2007

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Considerable effort is usually expended on optimizing the layout of semiconductor devices to minimize their area. This strategy boosts the number of die per wafer and hence minimizes the unit die cost. CMOS image sensors are subject to different economics because a lens train and a protective cover for the imager die are integral to solid state camera modules and their assembly processes. These considerations dictate that the silicon layout must be compromised in order to achieve the lowest cost and smallest form factor camera modules.

Solid-State Optical Sensors

Solid state optical sensors are finding application in an ever-widening variety of products. The largest markets by volume are camera modules for mobile phones, optical mice and digital cameras (see Figure 1). Solid state optical sensors are also utilized in large quantities in Web cams, document copiers, bar code readers, camcorders and positional control systems. These are large markets, which are growing rapidly, many exhibiting compound annual growth rates in double digits [Prismark, 2006]. More than two million cameras are made daily purely for inclusion in mobile phones.

Figure 1: The five largest markets for solid state image sensors in 2005.

The majority of solid state image sensors are based on complementary metal-oxide semiconductor (CMOS) technology as this provides a more integrated solution than competing approaches like CCD (Charged-Coupled Device).

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